1. Field of the Invention
The present invention relates to an operational amplifier circuit. More particularly, the present invention relates to a technique of correcting an output offset voltage of a fully differential folded amplifier circuit.
Priority is claimed on Japanese Patent Application No. 2011-005699, filed Jan. 14, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
A fully differential amplifier circuit can obtain great output amplitude and avoid poles generated in a gate of an active load. Accordingly, a high-speed closed loop characteristic can be obtained. The fully differential amplifier circuit has a higher performance than a single-ended amplifier circuit. However, common mode feedback is necessary in order to stabilize an output voltage. Common mode feedbacks are classified into several feedbacks depending on detection schemes and feedback destinations. Common mode signal detection schemes include a resistor division scheme, a dual differential pair scheme, a linear MOS resistor scheme, etc. A detected error signal is fed back to a tail current source of a differential pair or an active load. Common mode feedback allows a fully differential amplifier circuit to output a signal using a reference voltage as a center.
A common mode feedback method for a fully differential folded amplifier circuit is disclosed in Japanese Unexamined Patent Application, First Publication No. 2008-125024. FIGS. 4 and 5 are circuit diagrams disclosed in Japanese Unexamined Patent Application, First Publication No. 2008-125024. FIG. 4 is a block diagram illustrating a schematic configuration of an operational amplifier circuit. FIG. 5 is a circuit diagram illustrating a detailed configuration of the operational amplifier circuit.
The operational amplifier circuit of FIG. 4 includes a transconductance amplifier circuit 1, an output load ZL, a common mode feedback circuit 2, and a voltage supply circuit 3.
The transconductance amplifier circuit 1 converts a differential input voltage into a differential output current. The output load ZL is connected between output terminals of the operational amplifier circuit. The differential output current of the transconductance amplifier circuit 1 is applied to the output load ZL, which outputs a differential output voltage corresponding to the differential output current. The differential output voltage of the transconductance amplifier circuit 1 generated in the output load ZL and a base voltage vref are input to the common mode feedback circuit 2. The common mode feedback circuit 2 outputs a control signal to the transconductance amplifier circuit 1 so that a DC voltage level of the differential output voltage of the transconductance amplifier circuit 1 generated in the output load ZL is the same as the base voltage vref. The voltage supply circuit 3 supplies the base voltage vref to the common mode feedback circuit 2.
Details of the circuit shown in FIG. 4 are shown in FIG. 5. The transconductance amplifier circuit 1 includes current sources I1, I2, I3, I4, I5, I6, and I7 and transistors M1, M2, M3, and M4. The output load ZL includes a resistor RL and a capacitor CL. The common mode feedback circuit 2 includes current sources I8, I9, and I10, and transistors M5, M6, M7, M8, M9, M10, M11, M12, M13, and M14. The voltage supply circuit 3 includes transistors M15 and M16.
An operation of the circuit illustrated in FIG. 5 will be described. The differential output current output from the transconductance amplifier circuit 1 is converted into a voltage signal by the resistor RL. The voltage signal converted by the resistor RL is input to the transistors M5 and M7. The voltage input to the transistors M5 and M7 is converted into an average value of the two voltages, i.e., a common mode output voltage by the current sources I8 and I9 and the transistors M5, M6, M7, M8, M11, and M12, and input to the transistor M9. The current source I10 and the transistors M9, M10, M13, and M14 change a current flowing in the transistor M14 according to a difference between the voltage input to the transistor M9 and the base voltage generated by the transistor M15 and the transistor M16 and input to the transistor M10. The current flowing in the transistor M14 is copied to the transistors M3 and M4 constituting a current mirror and the output current of the transconductance amplifier circuit 1 is adjusted. The above-described operation enables the common mode output voltage of the transconductance amplifier circuit 1 to be the same as the base voltage.
However, in the configuration disclosed in the above-described Japanese Unexamined Patent Application, First Publication No. 2008-125024, an output offset voltage is generated in the common mode output voltage due to a current error of the current source or an error caused by current mirror precision of a current mirror even though the common mode feedback is provided. Thereby, the common mode output voltage does not match the base voltage, and an output amplitude range becomes narrower.